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Application Note 9822
The evaluation board provides a single-ended to differential
analog front-end for converting the typical laboratory signal
generators 50 ? single-ended output to a differential input
signal for the converters differential-in-differential-out
sample-and-hold front end. The evaluation boards analog
front end is implemented utilizing two Intersil HFA1109
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. HI5767EVAL1 EVALUATION BOARD POWER
SUPPLIES
450MHz, low power, current feedback video operational
amplifiers. One operational amplifier of the analog front-
end, U3, is configured in a unity gain configuration, A V = 1,
driving the non-inverting input of the converter while the
second operational amplifier, U4, is configured in an
POWER
SUPPLY
+5VAIN
NOMINAL
VALUE
5.0V ± 5%
CURRENT
(TYP)
26mA
FUNCTION(S)
SUPPLIED
Analog Input and
External Reference
Voltage Operational
Amplifiers, Bandgap
inverting-gain of one, A V = -1, configuration driving the
Reference
inverting input of the converter. The input of this analog
-5VAIN
-5.0V ± 5%
24mA
Analog Input and
front-end, RF SMA connector J1, is AC coupled and
provides a termination impedance of 50 ? . It should be
pointed out that provision for increasing the gain of the
External Reference
Voltage Operational
Amplifiers
single-ended to differential analog front-end has been
provided. For the non-inverting amplifier a location for R3 is
+5VA1IN
+5VDIN
5.0V ± 5%
5.0V ± 5%
50mA
63mA
A/D AV CC
Sample Clock
present but not utilized for the unity gain configuration but
Generation
could be installed to change the gain of this amplifier. Of
course, it would also be necessary to match the magnitude
of the new gain in the inverting amplifier signal path. It is
+5VD1IN
+5VD2IN
5.0V ± 5%
3.0V ± 10%
20mA
5mA
A/D DV CC1
A/D DV CC2
recommended that the user refer to the HFA1109 data
sheets and application notes for specific details on making
any changes to these amplifier configurations.
Evaluation Board Layout and Power
Supplies
The HI5767 evaluation board is a four layer board with a
layout optimized for the best performance of the converter.
This application note includes an electrical schematic of the
evaluation board, a component parts list, a component
placement layout drawing and reproductions of the various
board layers used in the board stack-up. The user should
feel free to copy the layout in their application.
The HI5767 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies are
hooked up with the twisted pair wires soldered to the plated
through holes marked +5VAIN, +5VA1IN, -5VAIN, +5VDIN,
+5VD1IN, +5VD2IN, AGND and DGND near the
prototyping area. +5VDIN, +5VD1IN and +5VD2IN are
digital supplies and are returned to DGND. +5VAIN,
+5VA1IN and -5VAIN are the analog supplies and are
returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
3-3
Sample Clock Driver
In order to ensure rated performance of the HI5767, the duty
cycle of the sample clock should be held at 50% ± 5%. It must
also have low phase noise and operate at standard TTL levels.
It can be dif?cult to ?nd a low phase noise generator that will
provide a 60MHz squarewave at TTL logic levels.
Consequently, the HI5767EVAL1 evaluation board is
designed with a logic inverter (U5) acting as a voltage
comparator to generate the sampling clock for the HI5767
when a sinewave (< ± 1.5V) is applied to the AC-coupled, 50 ?
terminated CLK input through SMA type RF connector, J2,
of the evaluation board. The sample clock sinewave is AC
coupled into the input of the inverter and a discrete bias tee
is used to bias the sinewave around the trigger level of the
inverter’s input. A potentiometer (VR2) varies the DC bias
voltage added to the sinewave input allowing the user to
adjust the duty cycle of the sampling clock to obtain the best
performance from the ADC and to evaluate the effects of
sample clock duty cycle on the performance of the converter.
The trigger level for the sample clock input to the HI5767
converter is approximately 1.5V. Therefore, the duty cycle of
the sampling clock should be measured at the 1.5V trigger
level of the HI5767 sample clock input pin.
The sinewave to logic level comparator drives a series of
additional inverters that provide isolation between the three
sample clocks used on the evaluation board. One clock is
used to drive the converter sample clock input pin and the
other two provide CLK and CLK at the data output
header/connector, P2. The clock/data relationship at the P2
output connector is as follows. CLK has rising edges aligned
with digital data transitions and CLK has rising edges
aligned mid-bit.
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